Semiconductor device having doped seed layer and method of manufacturing the same

ABSTRACT

A semiconductor device includes a substrate and a seed layer over the substrate. The seed layer includes a first seed sublayer having a first lattice structure, wherein the first seed sublayer includes AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm. The semiconductor device further includes a graded layer over the seed layer. The graded layer includes a first graded sublayer including AlGaN, having a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN having a second Al:Ga ratio. The semiconductor device further includes a two-dimensional electron gas (2-DEG) over the graded layer.

PRIORITY CLAIM

The present application is a continuation of U.S. application Ser. No.17/074,952, filed Oct. 20, 2020, which is a continuation of U.S.application Ser. No. 16/687,219, filed Nov. 18, 2019, now U.S. Pat. No.11,329,148, issued May 10, 2022, which is a continuation of U.S.application Ser. No. 14/158,157, filed Jan. 17, 2014, now U.S. Pat. No.10,483,386, issued Nov. 19, 2019, which are incorporated herein byreference in their entireties.

RELATED APPLICATIONS

The instant application is related to the following U.S. patentapplications:

-   U.S. patent application Ser. No. 13/944,713; filed Jul. 17, 2013,    now U.S. Pat. No. 9,093,511, issued Jul. 25, 2015;-   U.S. patent application Ser. No. 13/944,494, filed Jul. 17, 2013,    now U.S. Pat. No. 8,901,609. Issued Dec. 2, 2014; and-   U.S. patent application Ser. No. 13/944,625, filed Jul. 17, 2013,    now U.S. Pat. No. 8,866,192, issued Oct. 21, 2014.

The entire contents of the above-referenced applications areincorporated by reference herein.

BACKGROUND

In semiconductor technology, Group III-Group V (or III-V) semiconductorcompounds are used to form various integrated circuit devices, such ashigh power field-effect transistors, high frequency transistors, highelectron mobility transistors (HEMTs), or metal-insulator-semiconductorfield-effect transistors (MISFETs). A HEMT is a field effect transistorincorporating a junction between two materials with different band gaps(i.e., a heterojunction) as the channel instead of a doped region, as isgenerally the case for metal oxide semiconductor field effecttransistors (MOSFETs). In contrast with MOSFETs, HEMTs have a number ofattractive properties including high electron mobility and the abilityto transmit signals at high frequencies, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are illustrated by way of example, and not bylimitation, in the figures of the accompanying drawings, whereinelements having the same reference numeral designations represent likeelements throughout. It is emphasized that, in accordance with standardpractice in the industry various features may not be drawn to scale andare used for illustration purposes only. In fact, the dimensions of thevarious features in the drawings may be arbitrarily increased or reducedfor clarity of discussion. The drawings, which are incorporated herein,include the following in which:

FIG. 1 is a cross-sectional view of a high electron mobility transistor(HEMT) in accordance with one or more embodiments;

FIG. 2 is a flow chart of a method of making an HEMT in accordance withone or more embodiments;

FIGS. 3A-3D are cross-sectional view of a HEMT at various stages ofproduction in accordance with one or more embodiments;

FIG. 4 is a cross-sectional view of an enhanced HEMT (E-HEMT) inaccordance with one or more embodiments;

FIG. 5 is a cross-sectional view of a depletionmetal-insulator-semiconductor field-effect transistor (D-MISFET) inaccordance with one or more embodiments; and

FIG. 6 is a cross-sectional view of an enhancedmetal-insulator-semiconductor field-effect transistor (E-MISFET) inaccordance with one or more embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are examples and are not intended to belimiting.

FIG. 1 is a cross-sectional view of a high electron mobility transistor(HEMT) 100 in accordance with one or more embodiments. HEMT 100 includesa substrate 102. A seed layer 104 is over substrate 102. In someembodiments, seed layer 104 includes multiple layers. A graded layer 106is over seed layer 104. A channel layer 108 is over graded layer 106. Anactive layer 110 is over channel layer 108. Due to a band gapdiscontinuity between channel layer 108 and active layer 110, a twodimension electron gas (2-DEG) 112 is formed in the channel layer nearan interface with the active layer. Electrodes 114 are over channellayer 108 and a gate 116 is over active layer 110 between theelectrodes.

Substrate 102 acts as a support for HEMT 100. In some embodiments,substrate 102 is a silicon substrate. In some embodiments, substrate 102includes silicon carbide (SiC), sapphire, or another suitable substratematerial. In some embodiments, substrate 102 is a silicon substratehaving a (111) lattice structure. In some embodiments, substrate 102 isdoped.

In some embodiments, substrate 102 is doped with p-type dopants. In someembodiments, the p-type dopants include boron, aluminum, gallium,indium, titanium, boron di-fluoride, combinations thereof, or othersuitable p-type dopants. The dopant concentration ranges from about1×10¹⁸ ions/cm³ to about 1×10²³ ions/cm³. In some embodiments, thep-type dopants are implanted using an ion implantation process toimplant dopants directly into substrate 102. In some embodiments, thep-type dopants are introduced using a plasma enhanced chemical vaporetching (PECVE) process, a reactive ion etching (RIE) process, an ionimplantation (IMP) or another suitable material removal process toremove a top portion of substrate 102 and then a doped layer is grownover the remaining portion of the substrate. In some embodiments, ananneal process is performed following the introduction of the p-typedopants. In some embodiments, the anneal process is performed at atemperature ranging from about 900° C. to about 1100° C., for a durationof up to 60 minutes.

The introduction of the p-type dopants helps to reduce a concentrationof electrons present at a top surface of the substrate. The lowerelectron concentration enables a higher voltage to be applied to gate116 without damaging HEMT 100. As a result, HEMT 100 is able to be usedin higher voltage applications in comparison with HEMTs which do notinclude substrate 102 having a doped top surface, as described above.

Seed layer 104 helps to compensate for a mismatch in lattice structuresbetween substrate 102 and graded layer 106. In some embodiments, seedlayer 104 includes multiple layers. In some embodiments, seed layer 104includes a same material formed at different temperatures. In someembodiments, seed layer 104 includes a step-wise change in latticestructure. In some embodiments, seed layer 104 includes a continuouschange in lattice structure. In some embodiments, seed layer 104 isformed by epitaxially growing the seed layer on substrate 102.

Seed layer 104 is doped with carbon. In some embodiments, aconcentration of carbon dopants ranges from about 2×10¹⁷ atoms/cm³ toabout 1×10²⁰ atoms/cm³. In some embodiments, seed layer 104 is dopedusing an ion implantation process. In some embodiments, seed layer 104is doped using an in-situ doping process. In some embodiments, seedlayer 104 is formed using molecular oriented chemical vapor deposition(MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy(HVPE), atomic layer deposition (ALD), physical vapor deposition (PVD)or another suitable formation process. In some embodiments, the in-situdoping process includes introducing the carbon dopants during formationof seed layer 104. In some embodiments, a source of the carbon dopantsincludes a hydrocarbon (C_(c)H_(y)) such as CH₄, C₇H₇, C₁₆H₁₀, oranother suitable hydrocarbon. In some embodiments, the source of thecarbon dopants includes CBr₄, CCl₄, or another suitable carbon source.

Doping seed layer 104 with carbon helps to trap silicon atoms to helpprevent the silicon atoms from substrate 102 from diffusing into gradedlayer 106. By trapping the silicon atoms, an inversion current withinHEMT 100 is reduced in comparison with HEMTs which do not include carbonin seed layer. The inversion current causes an HEMT to experiencedegradation in performance over time due to silicon diffusion into seedlayer 104. The carbon dopants occupy locations in a lattice structure ofseed layer 104 which would enable silicon atoms to diffuse into the seedlayer, thus reducing a number of available diffusion routes for siliconinto the seed layer.

In at least one example, seed layer 104 includes a first layer ofaluminum nitride (AlN) and a second layer of AlN over the first layer ofAlN. The second layer of AlN is formed at a high temperature, rangingfrom about 1000° C. to about 1300° C., and has a thickness ranging fromabout 50 nanometers (nm) to about 200 nm. If the thickness of the firstlayer of AlN is too small, subsequent layers formed on the first layerof AlN will experience a high stress at the interface with the first AlNlayer due to lattice mismatch increasing a risk of layer separation. Ifthe thickness of the first layer of AlN is too great, the material iswasted and production costs increase. The first layer of AlN is formedat a low temperature, ranging from about 900° C. to about 1000° C., andhas a thickness ranging from about 20 nm to about 80 nm. The lowertemperature provides a different lattice structure in the second AlNlayer in comparison with the first AlN layer. The lattice structure inthe second AlN layer is more different from a lattice structure ofsubstrate 102 than the first AlN layer. If the thickness of the secondlayer of AlN is too small, subsequent layers formed on the second layerof AlN will experience a high stress at the interface with the secondlayer of AlN due to lattice mismatch increasing the risk of layerseparation. If the thickness of the second layer of AlN is too great,the material is wasted and production costs increase.

Graded layer 106 provides additional lattice matching between seed layer104 and channel layer 108. In some embodiments, graded layer 106 isdoped with p-type dopants to reduce the risk of electron injection fromsubstrate 102. Electron injection occurs when electrons from substrate102 diffuse into channel layer 108. By including p-type dopants, theelectrons are trapped by the positively charged dopants and do notnegatively impact performance of 2-DEG 112 in channel layer 108. In someembodiments, the p-type dopant concentration in graded layer 106 isgreater than or equal to 1×10¹⁷ ions/cm³. In some embodiments, thep-type dopants include carbon, iron, magnesium, zinc or other suitablep-type dopants. In some embodiments, graded layer 106 includes aluminumgallium nitride (Al_(x)Ga_(1-x)N), where x is the aluminum content ratioin the graded layer. In some embodiments, the graded layer includesmultiple layers each having a decreased ratio x (from a layer adjoiningseed layer 104 to a layer that adjoins SLS 108, or from the bottom tothe top portions of the graded layer). In some embodiments, graded layerhas a thickness ranging from about 550 nm to about 1050 nm. If gradedlayer 106 is too thin, electrons from substrate 102 will be injectedinto channel layer 110 at high voltages, negatively impacting 2-DEG 112or a lattice mismatch between seed layer 104 and channel layer 108 willresult in a high stress in the channel layer and increase a risk oflayer separation. If graded layer 106 is too thick, material is wastedand production costs increase. In some embodiments, the graded layer isformed at a temperature ranging from about 1000° C. to about 1200° C. Insome embodiments, a p-type dopant concentration of graded layer 106increases from a bottom of the graded layer to a top of the gradedlayer.

In at least one example, graded layer 106 includes three graded layers.A first graded layer adjoins seed layer 104. The first graded layerincludes Al_(x)Ga_(1-x)N, where x ranges from about 0.7 to about 0.9. Athickness of the first graded layer ranges from about 50 nm to about 200nm. A second graded layer is on the first graded layer. The secondgraded layer includes Al_(x)Ga_(1-x)N, where x ranges from about 0.4 toabout 0.6. A thickness of the second graded layer ranges from about 150nm to about 250 nm. A third graded layer is on the second graded layer.The third graded layer includes Al_(x)Ga_(1-x)N, where x ranges fromabout 0.15 to about 0.3. A thickness of the third graded layer rangesfrom about 350 nm to about 600 nm.

Channel layer 108 is used to help form a conductive path for selectivelyconnecting electrodes 114. In some embodiments, channel layer 108 has adopant concentration of p-type dopants of less than or equal to 1×10¹⁷ions/cm³. In some embodiments, channel layer 108 includes undoped GaN.In some embodiments, channel layer 108 has a thickness ranging fromabout 0.5 μm to about 5.0 μm. If a thickness of channel layer 108 is toothin, the channel layer will not provide sufficient charge carriers toallow HEMT 100 to function properly. If the thickness of channel layer108 is too great, material is wasted and production costs increase. Insome embodiments, channel layer 108 is formed by an epitaxial process.In some embodiments, channel layer 108 is formed at a temperatureranging from about 1000° C. to about 1200° C.

Active layer 110 is used to provide the band gap discontinuity withchannel layer 108 to form 2-DEG 112. In some embodiments, active layer110 includes AlN. In some embodiments, active layer 110 includes a mixedstructure, e.g., Al_(x)Ga_(1-x)N, where x ranges from about 0.1 to 0.3.In some embodiments where active layer 110 includes an AlN layer and amixed structure layer, a thickness of the AlN layer ranges from about0.5 nm to about 1.5 nm. If active layer 110 is too thick, selectivelycontrolling the conductivity of the channel layer is difficult. Ifactive layer 110 is too thin, an insufficient amount of electrons areavailable for 2-DEG 112. In some embodiments, active layer 110 is formedusing an epitaxial process. In some embodiments, active layer 110 isformed at a temperature ranging from about 1000° C. to about 1200° C.

2-DEG 112 acts as the channel for providing conductivity betweenelectrodes 114. Electrons from a piezoelectric effect in active layer110 drop into channel layer 108, and thus create a thin layer of highlymobile conducting electrons in the channel layer.

Electrodes 114 act as a source and a drain for HEMT 100 for transferringa signal into or out of the HEMT. Gate 116 helps to modulateconductivity of 2-DEG 112 for transferring the signal between electrodes114.

HEMT 100 is normally conductive meaning that a positive voltage appliedto gate 116 will reduce the conductivity between electrodes 114 along2-DEG 112.

FIG. 2 is a flow chart of a method 200 of making an HEMT in accordancewith one or more embodiments. Method 200 begins with operation 202 inwhich a low temperature (LT) seed layer and a high temperature (HT) seedlayer are formed on a substrate, e.g., substrate 102. The LT seed layeris formed on the substrate and the HT seed layer is formed on the LTseed layer.

In some embodiments, LT seed layer and HT seed layer include AlN. Insome embodiments, the formation of LT seed layer and HT seed layer areperformed by an epitaxial growth process. In some embodiments, theepitaxial growth process includes a metal-organic chemical vapordeposition (MOCVD) process, a molecular beam epitaxy (MBE) process, ahydride vapor phase epitaxy (HVPE) process or another suitable epitaxialprocess. In some embodiments, the MOCVD process is performed usingaluminum-containing precursor and nitrogen-containing precursor. In someembodiments, the aluminum-containing precursor includestrimethylaluminium (TMA), triethylaluminium (TEA), or other suitablechemical. In some embodiments, the nitrogen-containing precursorincludes ammonia, tertiarybutylamine (TBAm), phenyl hydrazine, or othersuitable chemical. In some embodiments, the LT seed layer or the HT seedlayer includes a material other than AlN. In some embodiments, the HTseed layer has a thickness ranging from about 50 nm to about 200 nm. Insome embodiments, the HT seed layer is formed at a temperature rangingfrom about 1000° C. to about 1300° C. In some embodiments, the LT seedlayer has a thickness ranging from about 20 nm to about 80 nm. In someembodiments, the LT seed layer is formed at a temperature ranging fromabout 900° C. to about 1000° C.

FIG. 3A is a cross-sectional view of a HEMT following operation 202. TheHEMT includes seed layer 104 on substrate 102. Seed layer 104 includes aHT seed layer 104 a on substrate 102 and a LT seed layer 104 b on the HTseed layer.

In operation 204, the seed layer is doped with carbon. In someembodiments, the seed layer is doped to a carbon dopant concentrationranging from about 2×10¹⁷ atoms/cm³ to about 1×10²⁰ atoms/cm³. In someembodiments, the seed layer is doped using ion implantation process. Insome embodiments, the ion implantation process is performed at animplantation energy ranging from about 30 kilo-electron volts (KeV) toabout 150 (KeV). In some embodiments, the ion implantation process isperformed using an implantation angle ranging from about 5-degrees toabout 10-degrees. In some embodiments, the seed layer is doped using anin-situ doping process. In some embodiments, operations 202 and 204 arecombined into a single operation. In some embodiments, at least onelayer of the seed layer is formed using MOCVD, MBE, ALD, PVD or anothersuitable formation process. In some embodiments, the in-situ dopingprocess includes introducing the carbon dopants during formation of atleast one layer of the seed layer. In some embodiments, the carbondopants are introduced using a carbon source including a hydrocarbon(C_(x)H_(y)) such as CH₄, C₇H₇, C₁₆H₁₀, or another suitable hydrocarbon.In some embodiments, the carbon is introduced using an ion implantationprocess and a hydrocarbon as a carbon source. In some embodiments, thecarbon dopants are introduced using a carbon source including a carbonhalide, such as CBr₄, CCl₄, or another suitable carbon source. In someembodiments, the carbon is introduced using an in-situ process and acarbon halide as a carbon source.

FIG. 3B is a cross-sectional view of a HEMT following operation 204. TheHEMT includes seed layer 104 on substrate 102. Seed layer 104 is dopedusing a dopant process 302. Dopant process 302 introduces carbon intoseed layer 104.

Returning to FIG. 2 , method 200 continues with operation 206 in which agraded layer is formed on the LT seed layer. In some embodiments, thegraded layer includes an aluminum-gallium nitride (Al_(x)Ga_(1-x)N)layer. In some embodiments, the graded aluminum gallium nitride layerhas two or more aluminum-gallium nitride layers each having a differentratio x decreased from the bottom to the top. In some embodiments, eachof the two or more aluminum-gallium nitride layers is formed byperforming an epitaxial process. In some embodiments, the epitaxialprocess includes a MOCVD process, an MBE process, a HVPE process oranother suitable epitaxial process. In some embodiments, the MOCVDprocess uses an aluminum-containing precursor, a gallium-containingprecursor, and a nitrogen-containing precursor. In some embodiments, thealuminum-containing precursor includes TMA, TEA, or other suitablechemical. In some embodiments, the gallium-containing precursor includestrimethylgallium (TMG), triethylgallium (TEG), or other suitablechemical. In some embodiments, the nitrogen-containing precursorincludes ammonia, TBAm, phenyl hydrazine, or other suitable chemical. Insome embodiments, the graded aluminum gallium nitride layer has acontinuous gradient of the ratio x gradually decreased from the bottomto the top. In some embodiments, x ranges from about 0.5 to about 0.9.In some embodiments, the graded layer is formed at a temperature rangingfrom about 1000° C. to about 1200° C. In some embodiments, the gradedlayer is doped with p-type dopants, such as carbon, iron, magnesium,zinc or other suitable p-type dopants.

In at least one embodiment, a first graded layer is formed on the LTseed layer. The first graded layer adjoins seed layer 104. The firstgraded layer includes Al_(x)Ga_(1-x)N, where x ranges from about 0.7 toabout 0.9. A thickness of the first graded layer ranges from about 50 nmto about 200 nm. In some embodiments, the first graded layer is formedusing epitaxy. In some embodiments, the first graded layer is formed ata temperature ranging from about 1000° C. to about 1200° C. A secondgraded layer is formed on the first graded layer. The second gradedlayer includes Al_(x)Ga_(1-x)N, where x ranges from about 0.4 to about0.6. A thickness of the second graded layer ranges from about 150 nm toabout 250 nm. In some embodiments, the second graded layer is formedusing epitaxy. In some embodiments, the second graded layer is formed ata temperature ranging from about 1000° C. to about 1200° C. A thirdgraded layer is formed on the second graded layer. The third gradedlayer includes Al_(x)Ga_(1-x)N, where x ranges from about 0.15 to about0.3. A thickness of the third graded layer ranges from about 350 nm toabout 600 nm. In some embodiments, the third graded layer is formedusing epitaxy. In some embodiments, the third graded layer is formed ata temperature ranging from about 1000° C. to about 1200° C.

In operation 208, a channel layer is formed on the graded layer. In someembodiments, the channel layer includes p-type dopants. In someembodiments, the channel layer includes GaN, and the P-type doping isimplemented by using dopants including carbon, iron, magnesium, zinc orother suitable p-type dopants. In some embodiments, the channel layer isformed by performing an epitaxial process. In some embodiments, theepitaxial process includes a MOCVD process, an MBE process, a HVPEprocess or another suitable epitaxial process. In some embodiments, thechannel layer has a thickness ranging from about 0.2 μm to about 1.0 μm.In some embodiments, the dopant concentration in the channel layer isequal to or less than about 1×10¹⁷ ions/cm³. In some embodiments, thechannel layer is undoped. In some embodiments, the channel layer isformed at a temperature ranging from about 1000° C. to about 1200° C.

FIG. 3C is a cross-sectional view of a HEMT following operation 208. TheHEMT includes graded layer 106 on seed layer 104. For the sake ofsimplicity, seed layer 104 and graded layer 106 are shown as singlelayers in the remaining cross-sectional views. Channel layer 108 is alsoon graded layer 106.

Returning to FIG. 2 , in operation 210 an active layer is formed on thechannel layer. In some embodiments, the active layer includes AlN,Al_(x)Ga_(1-x)N, combinations thereof or other suitable materials. Insome embodiments, x ranges from about 0.1 to about 0.3. In someembodiments, the active layer is formed by performing an epitaxialprocess. In some embodiments, the epitaxial process includes a MOCVDprocess, an MBE process, a HVPE process or another suitable epitaxialprocess. In some embodiments, the active layer has a thickness rangingfrom about 10 nm to about 40 nm. In some embodiments where the activelayer includes both AlN and Al_(x)Ga_(1-x)N, the AlN layer has athickness ranging from about 0.5 nm to about 1.5 nm and theAl_(x)Ga_(1-x)N layer has a thickness ranging from about 10 nm to about40 nm. In some embodiments, the active layer is formed at a temperatureranging from about 1000° C. to about 1200° C.

FIG. 3D is a cross-sectional view of the HEMT following operation 210 inaccordance with one or more embodiments. The HEMT includes active layer110 on channel layer 108. 2-DEG 112 is formed in channel layer 108 dueto the band gap discontinuity between active layer 110 and the channellayer.

Returning to FIG. 2 , in operation 212 electrodes and a gate are formedon the active layer. The electrodes are formed over the other portion ofthe channel layer, and the gate is formed over the active layer. In someembodiments, a patterned mask layer (i.e., a photoresistive layer) isformed on the upper surface of the active layer, and an etching processis performed to remove a portion of the active layer to form openingspartially exposing an upper surface of the other portion of the channellayer. A metal layer is then deposited over the patterned active layerand fills the openings and contacts the other portion of the channellayer. Another patterned photoresist layer is formed over the metallayer, and the metal layer is etched to form the electrodes over theopenings and the gate over the upper surface of the active layer. Insome embodiments, the metal layer for forming the electrodes or the gateincludes one or more conductive materials. In some embodiments, theelectrodes or the gate include one or more layers of conductivematerials. In at least one embodiment, the electrodes or the gateinclude at least one barrier layer contacting the other portion of thechannel layer and/or the active layer.

Following operation 212, the HEMT has a structure similar to HEMT 100.

FIG. 4 is a cross-sectional view of an enhanced HEMT (E-HEMT) 400 inaccordance with one or more embodiments. E-HEMT 400 is similar to HEMT100. Similar elements have a same reference number as HEMT 100 increasedby 300. In comparison with HEMT 100, E-HEMT 400 includes a semiconductormaterial 420 between gate 416 and active layer 410. In some embodiments,semiconductor material 420 is a group III-V semiconductor material suchas GaN, AlGaN, InGaN, or another suitable group III-V semiconductormaterial. In some embodiments, semiconductor material 420 is doped withp-type or n-type dopants. In some embodiments, the p-type dopantsinclude carbon, iron, magnesium, zinc or other suitable p-type dopants.In some embodiments, the n-type dopants include silicon, oxygen or othersuitable n-type dopants. In comparison with HEMT 100, E-HEMT 400 isnormally non-conductive between electrodes 414. As a positive voltage isapplied to gate 416, E-HEMT 400 provides an increased conductivitybetween electrodes 414.

FIG. 5 is a cross-sectional view of a depletionmetal-insulator-semiconductor field-effect transistor (D-MISFET) 500 inaccordance with one or more embodiments. D-MISFET 500 is similar to HEMT100. Similar elements have a same reference number as HEMT 100 increasedby 400. In comparison with HEMT 100, D-MISFET 500 includes a dielectriclayer 530 between gate 516 and active layer 510. In some embodiments,dielectric layer 530 includes silicon dioxide. In some embodiments,dielectric layer 530 includes a high-k dielectric layer having adielectric constant greater than a dielectric constant of silicondioxide. Similar to HEMT 100, D-MISFET 500 is normally conductivebetween electrodes 514. As a positive voltage is applied to gate 516,D-MISFET 500 provides a decreased conductivity between electrodes 514.

FIG. 6 is a cross-sectional view of an enhancedmetal-insulator-semiconductor field-effect transistor (E-MISFET) 600 inaccordance with one or more embodiments. E-MISFET 600 is similar to HEMT100. Similar elements have a same reference number as HEMT 100 increasedby 500. In comparison with HEMT 100, E-MISFET 600 gate 616 is in contactwith channel layer 608 without intervening active layer 610. E-MISFET600 further includes a dielectric layer 630 between gate 616 and channellayer 608. Dielectric layer 630 also separates sidewalls of gate 616 andactive layer 610. In some embodiments, dielectric layer 630 includessilicon dioxide. In some embodiments, dielectric layer 630 includes ahigh-k dielectric layer having a dielectric constant greater than adielectric constant of silicon dioxide. In comparison with HEMT 100,E-MISFET 600 is normally non-conductive between electrodes 614. As apositive voltage is applied to gate 616, E-MISFET 600 provides anincreased conductivity between electrodes 614.

An aspect of this description relates to a semiconductor device. Thesemiconductor device includes a doped substrate. The semiconductordevice further includes a seed layer in direct contact with thesubstrate. The seed layer further includes a first seed sublayer havinga first lattice structure, wherein the first seed layer comprises AlN,and the first seed layer is doped with carbon. The seed layer furtherincludes a second seed sublayer over the first seed layer, wherein thesecond seed layer has a second lattice structure different from thefirst lattice structure. The semiconductor device further includes agraded layer in direct contact with the seed layer. The graded layerincludes a first graded sublayer including AlGaN, wherein the firstgraded sublayer has a first Al:Ga ratio; a second graded sublayer overthe first graded sublayer, wherein the second graded sublayer includesAlGaN, and the second graded sublayer has a second Al:Ga ratio differentfrom the first Al:Ga ratio; and a third graded sublayer over the secondgraded sublayer, wherein the third graded sub layer includes AlGaN, andthe third graded sublayer has a third Al:Ga ratio different from thesecond Al:Ga ratio. The semiconductor device further includes a channellayer over the graded layer, wherein a two-dimensional electron gas(2-DEG) is defined in the channel layer. The semiconductor devicefurther includes an active layer over the channel layer. In someembodiments, the semiconductor device further includes a gate over theactive layer. In some embodiments, the semiconductor device furtherincludes a source electrode in direct contact with the channel layer. Insome embodiments, the semiconductor device further includes a drainelectrode in direct contact with the channel layer. In some embodiments,the semiconductor device further includes a dielectric layer over theactive layer. In some embodiments, the dielectric layer covers anentirety of a topmost surface of the active layer. In some embodiments,the dielectric layer directly contacts the active layer. In someembodiments, the dielectric layer includes silicon dioxide. In someembodiments, the semiconductor device further includes a sourceelectrode, wherein the active layer directly contacts a sidewall of thesource electrode; and a drain electrode, wherein the active layerdirectly contacts a sidewall of the drain electrode.

An aspect of this description relates to a semiconductor device. Thesemiconductor device includes a substrate. The semiconductor deviceincludes a seed layer in direct contact with the substrate. The seedlayer includes a first seed sublayer having a first lattice structure,wherein the first seed sublayer comprises AlN, and the first seedsublayer is doped with carbon, and a second seed sublayer over the firstseed layer, wherein the second seed layer has a second lattice structuredifferent from the first lattice structure, and a thickness of thesecond seed sublayer ranges from about 50 nanometers (nm) to about 200nm. The semiconductor device further includes a graded layer in directcontact with the seed layer. The graded layer includes a first gradedsublayer including AlGaN, wherein the first graded sublayer has a firstAl:Ga ratio; and a second graded sublayer over the first gradedsublayer, wherein the second graded sublayer includes AlGaN, and thesecond graded sublayer has a second Al:Ga ratio different from the firstAl:Ga ratio. The semiconductor device further includes a two-dimensionalelectron gas (2-DEG) over the graded layer. In some embodiments, thesemiconductor device further includes a source electrode; a drainelectrode; and a gate, wherein the source electrode is closer to the2-DEG than the gate. In some embodiments, the semiconductor devicefurther includes a semiconductor layer between the gate and the 2-DEG.In some embodiments, the semiconductor device further includes adielectric layer between the gate and the 2-DEG. In some embodiments,the dielectric layer contacts a sidewall of the gate. In someembodiments, the 2-DEG is a normally conductive 2-DEG. In someembodiments, the 2-DEG is a normally non-conductive 2-DEG.

An aspect of this description relates to a method of making asemiconductor device. The method includes growing a first seed sublayerover a substrate, wherein the first seed sublayer comprises AlN. Themethod further includes doping the first seed sublayer with carbon. Themethod further includes growing a second seed sublayer over the dopedfirst seed sublayer, wherein the second seed sublayer comprises AlN, anda thickness of the second seed sublayer ranges from about 50 nanometers(nm) to about 200 nm. The method further includes growing a first gradedsublayer over the second seed sublayer, wherein the first gradedsublayer comprises AlGaN, and the first graded sublayer has a firstAl:Ga ratio. The method further includes growing a second gradedsublayer over the first graded sublayer, wherein the second gradedsublayer includes AlGaN, and the second graded sublayer has a secondAl:Ga ratio different from the first Al:Ga ratio. The method furtherincludes forming a two-dimensional electron gas (2-DEG) over the secondgraded sublayer. In some embodiments, the method further includesforming a gate over the 2-DEG. In some embodiments, forming the gatecauses the 2-DEG to be a normally conductive 2-DEG. In some embodiments,forming the gate causes the 2-DEG to be a normally non-conductive 2-DEG.In some embodiments, the method further includes forming a semiconductorlayer over the 2-DEG, wherein forming the gate comprises forming thegate over the semiconductor layer. In some embodiments, the methodfurther includes forming a dielectric layer over the 2-DEG, whereinforming the gate comprises forming the gate over the dielectric layer.In some embodiments, forming the gate includes forming the gate having asidewall in contact with the dielectric layer. In some embodiments,doping the first seed sublayer with carbon includes doping the firstseed sublayer using a carbon source selected from the group consistingof at least one of CH₄, C₇H₇, C₁₆H₁₀, CBr₄, and CC_(l4). In someembodiments, doping the first seed sublayer with carbon includesperforming an in-situ doping during the growing of the first seedsublayer.

An aspect of this description relates to a semiconductor device. Thesemiconductor device includes a substrate. The semiconductor devicefurther includes a seed layer in direct contact with the substrate. Theseed layer includes a first seed sublayer having a first latticestructure, wherein the first seed sublayer comprises AlN, and the firstseed sublayer is doped with carbon, and a second seed sublayer over thefirst seed layer, wherein the second seed layer has a second latticestructure different from the first lattice structure, and a thickness ofthe second seed sublayer ranges from about 50 nanometers (nm) to about200 nm. The semiconductor device further includes a graded layer indirect contact with the seed layer, wherein the graded layer comprises aplurality of layers of AlGaN, wherein each of the plurality of layers ofAlGaN has a different Al:Ga ratio for each other of the plurality oflayer of AlGaN. The semiconductor device further includes a selectivelyconductive two-dimensional electron gas (2-DEG) over the graded layer.In some embodiments, a dopant concentration of the carbon ranges from2×10¹⁷ atoms/cm³ to about 1×10²⁰ atoms/cm³. In some embodiments, thesemiconductor device further includes a semiconductor layer over theselectively conductive 2-DEG; and a gate over the semiconductor layer.In some embodiments, the semiconductor device further includes adielectric layer over the selectively conductive 2-DEG; and a gate overthe dielectric layer.

It will be readily seen by one of ordinary skill in the art that thedisclosed embodiments fulfill one or more of the advantages set forthabove. After reading the foregoing specification, one of ordinary skillwill be able to affect various changes, substitutions of equivalents andvarious other embodiments as broadly disclosed herein. It is thereforeintended that the protection granted hereon be limited only by thedefinition contained in the appended claims and equivalents thereof.

What is claimed is:
 1. A semiconductor device comprising: a substrate; a seed layer in direct contact with the substrate, wherein the seed layer comprises: a first seed sublayer having a first lattice structure, wherein the first seed sublayer comprises AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed sublayer, wherein the second seed sublayer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm; a graded layer in direct contact with the seed layer, wherein the graded layer comprises: a first graded sublayer including AlGaN, wherein the first graded sublayer has a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN, and the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and a two-dimensional electron gas (2-DEG) over the graded layer.
 2. The semiconductor device of claim 1, further comprising: a source electrode; a drain electrode; and a gate, wherein the source electrode is closer to the 2-DEG than the gate.
 3. The semiconductor device of claim 2, further comprising a semiconductor layer between the gate and the 2-DEG.
 4. The semiconductor device of claim 2, further comprising a dielectric layer between the gate and the 2-DEG.
 5. The semiconductor device of claim 4, wherein the dielectric layer contacts a sidewall of the gate.
 6. The semiconductor device of claim 1, wherein the 2-DEG is a normally conductive 2-DEG.
 7. The semiconductor device of claim 1, wherein the 2-DEG is a normally non-conductive 2-DEG.
 8. A method of making a semiconductor device, the method comprising: growing a first seed sublayer over a substrate, wherein the first seed sublayer comprises AlN; doping the first seed sublayer with carbon; growing a second seed sublayer over the doped first seed sublayer, wherein the second seed sublayer comprises AlN, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm; growing a first graded sublayer over the second seed sublayer, wherein the first graded sublayer comprises AlGaN, and the first graded sublayer has a first Al:Ga ratio; growing a second graded sublayer over the first graded sublayer, wherein the second graded sublayer comprises AlGaN, and the second graded sublayer has a second Al:Ga ratio different from the first Al:Ga ratio; and forming a two-dimensional electron gas (2-DEG) over the second graded sublayer.
 9. The method of claim 8, further comprising forming a gate over the 2-DEG.
 10. The method of claim 9, wherein forming the gate comprises causing the 2-DEG to be a normally conductive 2-DEG.
 11. The method of claim 9, wherein forming the gate comprises causing the 2-DEG to be a normally non-conductive 2-DEG.
 12. The method of claim 9, further comprising forming a semiconductor layer over the 2-DEG, wherein forming the gate comprises forming the gate over the semiconductor layer.
 13. The method of claim 9, further comprising forming a dielectric layer over the 2-DEG, wherein forming the gate comprises forming the gate over the dielectric layer.
 14. The method of claim 13, wherein forming the gate comprises forming the gate having a sidewall in contact with the dielectric layer.
 15. The method of claim 8, wherein doping the first seed sublayer with carbon comprises doping the first seed sublayer using a carbon source selected from the group consisting of at least one of CH₄, C₇H₇, C₁₆H₁₀, CBr₄, and CC_(l4).
 16. The method of claim 8, wherein doping the first seed sublayer with carbon comprises performing an in-situ doping during the growing of the first seed sublayer.
 17. A semiconductor device comprising: a substrate; a seed layer in direct contact with the substrate, wherein the seed layer comprises: a first seed sublayer having a first lattice structure, wherein the first seed sublayer comprises AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed sublayer, wherein the second seed sublayer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm; a graded layer in direct contact with the seed layer, wherein the graded layer comprises a plurality of layers of AlGaN, wherein each of the plurality of layers of AlGaN has a different Al:Ga ratio for each other of the plurality of layer of AlGaN; and a selectively conductive two-dimensional electron gas (2-DEG) over the graded layer.
 18. The semiconductor device of claim 17, wherein a dopant concentration of the carbon ranges from 2×10¹⁷ atoms/cm³ to about 1×10²⁰ atoms/cm³.
 19. The semiconductor device of claim 17, further comprising: a semiconductor layer over the selectively conductive 2-DEG; and a gate over the semiconductor layer.
 20. The semiconductor device of claim 17, further comprising: a dielectric layer over the selectively conductive 2-DEG; and a gate over the dielectric layer. 